1. Field of the Invention
The present invention relates generally to testing of semiconductors or other eletro-optical devices, and particularly to testing of bars, stacks or other arrays which are intermediate structures in the manufacture of chips.
2. Technical Background
Electro-optical devices, such as semiconductor lasers, have become important commercial components. They are used in a wide variety of applications ranging from the readout sources, using lasers, in compact disks to the transmitters in optical fiber communication systems. A semiconductor optical amplifier (SOA) is basically a laser without the mirrors to form the laser cavity. SOAs also have wide applications in optical communications, such as in amplification, arrays for ultra-fast switching, interconnection, wavelength conversion, and 2R-3R regeneration. The laser, SOA, and other components, such as modulators can be combined to form an intergrated device, such as a transmitter, transceiver, switch, regenerator, or integrated modulator chip.
While new applications in high-speed telecommunication networks continue to emerge, how to ensure that chips are reliable and manufacturable is the most challenging issue. One proven approach to this issue is to deploy tight quality control by using testing systems that characterize the device in many aspects.
Chips are manufactured on wafers or substrates which are processed and further divided into sections or quarters. The sections are further divided into bars or other arrays by breaking or cleaving the sections along the scribe lines. For use as a laser, the sections are cleaved to form facets along the elongated sides of the sections. The laser bar or array contain many laser diodes. Similarly, SOA chips are formed from the semiconductor section breaking along the scribe lines. To prevent the facets from acting as reflective mirrors, both of the cleaved facets of a SOAs are either coated with anti-reflection (AR) films or the facets are cleaved at an angle with respect to the SOA stripe. One SOA bar or section contains multiple SOAs, in quantity of 1 to 100 or more per each bar.
During the process of array or bar fabrication from the wafer to the final packaging of individual chips, the first stage where these chips exhibit both electrical and optical characteristics is when the bars or arrays are formed. Therefore, it is desired to characterize or otherwise screen for passing at this early stage by probing and testing all the chips, in a batch process, when they are still in the form of a bar or array. The chips or other devices that do not meet specifications will be scrapped before entering into further labor-costing or time-costing stages, i.e. packaging and life-testing or burn-in.
Usually, a full procedure of laser bar testing includes six measurements for each laser that is being probed: front-facet light versus current, back-facet light versus current, voltage versus current, horizontal far field pattern, vertical far field pattern and an optical spectrum analysis. A system that performs one or all of these measurement functions is called a laser bar tester.
The traditional practice of testing SOA involves using two optical fibers, one as input and the other as output. Light is injected into the SOA by the input fiber and the output light is collected from the SOA by the output fiber. The fiber-to-fiber parameters, e.g. optical gain, polarization dependent gain (PDG), gain tilt, and noise figure are measured. Therefore testing of SOA has been limited to fully- or partially-packaged devices, where the input fiber and output fiber are either permanently pigtailed or must be brought into precise proximity with the SOA. For the pigtailed case, a bad device means tremendous waste of material and labor hours per device; for the proximity case, the measurement throughput is low because aligning fibers to an SOA is very time consuming. The traditional fiber-fiber system is also costly to build and hard to maintain. A measurement system of high throughput that is capable of screening SOAs in the early fabrication stage is thus indispensable in order to reduce the cost, improve yield and provide quick feedback to design changes.
Therefore, there is a need to improve the semiconductor bar or array tester to minimize damage to the chips due to the testing process while maximizing efficiency.